(a) Technical Field
The present invention relates to a thin film transistor array panel and a method of manufacturing the same.
(b) Description of the Related Art
In general, flat panel displays such as liquid crystal displays or organic light emitting displays include a plurality of pairs of field generating electrodes and an electro-optical active layer interposed therebetween. In the case of liquid crystal displays, a liquid crystal layer is included as the electro-optical active layer, and in the case of organic light emitting displays, an organic emission layer is included as the electro-optical active layer.
One of the field generating electrodes of the pair is generally connected to a switching element and receives an electric signal, and an image is displayed by converting the electric signal to an optical signal by the electro-optical active layer.
In flat panel displays, a thin film transistor (TFT) that is a three terminal element is used as a switching element, and signal lines, such as a gate line transmitting a scanning signal for controlling the thin film transistor and a data line transmitting a signal to be applied to a pixel electrode, are used.
As the area displaying the image in display devices is increased, oxide semiconductor technology has been studied as a method that allows high-speed driving. Additionally, a method of reducing resistance in the signal lines has also been studied. Particularly, a main wiring layer may be formed of copper, a copper alloy, molybdenum, a molybdenum alloy, or the like in order to reduce the resistance of the signal lines. There is a problem, however, in that the characteristics of the thin film transistor that uses such wiring can deteriorate due to a reaction between the main wiring layer formed of metal and other layers in a process, and the like. For example, when a passivation layer including silicon oxide is formed after the main wiring layer is formed, charge mobility may be reduced due to oxidation of the main wiring layer material.
In order to prevent such problems, a capping layer including metal oxide may be formed between the main wiring layer and the passivation layer. But it is difficult to control an etching profile when a capping layer is used due to a difference between the etching speeds of the main wiring layer and the capping layer, and thus the resulting quality of the product may be poor due to problems that may occur during subsequent processing.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the disclosure and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art.